 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT533 Octal D-type transparent latch; 3-state; inverting Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state; inverting FEATURES * 3-state inverting outputs for bus oriented applications * Common 3-state output enable input * Output capability: bus driver * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT533 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT533 are octal D-type transparent latches featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all latches. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns 74HC/HCT533 The "533" consists of eight D-type transparent latches with 3-state inverting outputs. When LE is HIGH, data at the Dn inputs enter the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches. The "533" is functionally identical to the "373", "563" and "573", but the "373" and "573" have non-inverted outputs and the "563" and "573" have a different pin arrangement. TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay Dn to Qn LE to Qn CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". input capacitance power dissipation capacitance per latch notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 14 18 3.5 34 16 19 3.5 34 ns ns pF pF HCT UNIT December 1990 2 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state; inverting PIN DESCRIPTION PIN NO. 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 10 11 20 SYMBOL OE Q0 to Q7 D0 to D7 GND LE VCC NAME AND FUNCTION 74HC/HCT533 3-state output enable input (active LOW) 3-state latch outputs data inputs ground (0 V) latch enable input (active HIGH) positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 1990 3 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state; inverting FUNCTION TABLE INPUTS OPERATING MODES OE LE Dn enable and read register (transparent mode) latch and read register latch register and disable outputs Fig.4 Functional diagram. Notes L L H H L H 74HC/HCT533 INTERNAL OUTPUTS LATCHES Q TO Q 0 7 L H H L L L H H L L X X l h X X L H X X H L Z Z 1. H = HIGH voltage level h = HIGH voltage level one set-up prior to the HIGH-to-LOW LE transition L = LOW voltage level l = LOW voltage level one set-up prior to the HIGH-to-LOW LE transition X = don't care Z = high impedance OFF-state Fig.5 Logic diagram (one latch). Fig.6 Logic diagram. December 1990 4 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state; inverting DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER min. tPHL/ tPLH propagation delay Dn to Qn propagation delay LE to Qn 3-state output enable time OE to Qn 3-state output disable time OE to Qn output transition time +25 typ. 47 17 14 58 21 17 44 16 13 50 18 14 14 5 4 80 16 14 50 10 9 35 7 6 14 5 4 3 1 1 3 1 1 -40 to +85 max. min. 150 30 26 175 35 30 150 30 26 150 30 26 60 12 10 100 20 17 65 13 11 45 9 8 max. 190 38 33 220 44 37 190 38 33 190 38 33 75 15 13 120 24 20 75 15 13 55 11 9 -40 to +125 min. max. 225 45 38 265 53 45 225 45 38 225 45 38 90 18 15 ns 74HC/HCT533 TEST CONDITIONS UNIT V CC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.7 tPHL/ tPLH ns Fig.8 tPZH/ tPZL ns Fig.9 tPHZ/ tPLZ ns Fig.9 tTHL/ tTLH ns Fig.7 tW LE pulse width HIGH set-up time Dn to LE hold time Dn to LE ns Fig.8 tsu ns Fig.10 th ns Fig.10 December 1990 5 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state; inverting DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI Note to HCT types 74HC/HCT533 The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT Dn LE OE UNIT LOAD COEFFICIENT 0.15 0.30 0.55 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER min. tPHL/ tPLH tPHL/ tPLH tPZH/ tPZL tPHZ/ tPLZ tTHL/ tTLH tW tsu th propagation delay Dn to Qn propagation delay LE to Qn 3-state output enable time OE to Qn 3-state output disable time OE to Qn output transition time LE pulse width HIGH set-up time Dn to LE hold time Dn to LE 16 10 8 +25 typ. 19 22 19 18 5 5 3 2 max. 34 38 35 30 12 20 13 10 -40 to +85 min. max. 43 48 44 38 15 24 15 12 -40 to +125 min. max. 51 57 53 45 18 ns ns ns ns ns ns ns ns 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.7 Fig.8 Fig.9 Fig.9 Fig.7 Fig.8 Fig.10 Fig.10 UNIT V CC WAVEFORMS (V) TEST CONDITIONS December 1990 6 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state; inverting AC WAVEFORMS 74HC/HCT533 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the data input (Dn) to output (Qn) propagation delays and the output transition times. Fig.8 Waveforms showing the latch enable input (LE) pulse width, the latch enable input to output (Qn) propagation delays and the output transition times. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.10 Waveforms showing the data set-up and hold times for Dn input to LE input. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". Fig.9 Waveforms showing the 3-state enable and disable times. December 1990 7 |
Price & Availability of 74HC533
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |